Semiconductor Device Processing & Measuring Lab
National Tsing Hua University, Department of Engineering and System Science
Journal Papers
Enhanced Programming and Erasing Speeds of Charge-Trapping Flash Memory Device with Ge Channel
IEEE Electron Device Letters
Zong-Hao Ye, Kuei-Shu Chang-Liao, Li-Jung Liu, Jen-We Cheng, and Hsin-Kai Fang
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Gate Leakage Current Suppression and Reliability Improvement for Ultra-Low EOT Ge MOS Devices by Suitable HfAlO/HfON thickness and Sintering Temperature
Microelectronics Reliability
Wei-Fong Chi, Kuei-Shu Chang-Liao, Shih-Han Yi, Chen-Chien Li, and Yan-Lin Li
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Detection of Stress-Induced Interface Trap Generation on High-k gated nMOSFETs in Real Time by Stress-and-Sense Charge Pumping Technique
IEEE Trans. on Electron Devices
Chun-Chang Lu, Kuei-Shu Chang-Liao, Fu-Huan Tsai, Chen-Chien Li and Tien-Ko Wang
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A Highly Scalable Single Poly-Silicon Embedded Electrically Erasable Programmable Read Only Memory With Tungsten Control Gate by Full CMOS Process
IEEE Electron Device Letters
Chih-Ping Chung and Kuei-Shu Chang-Liao
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Electrical and Physical Characteristics of High-k Gated MOSFETs with In-situ H2O and O2 Plasma Formed Interfacial Layer
Microelectronic Engineering
Yan-Lin Li, Kuei-Shu Chang-Liao, Chen-Chien Li, Li-Ting Chen, Tzu-Hsiang Su, Yu-Wei Chang, Ting-Chun Chen, Chia-Chi Tsai, Chia-Hung Kao, Hao-Ting Feng, and Yao-Jen Lee
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Minimized Program Disturb for Vertically Stacked Junctionless Charge-Trapping Flash Memory Devices by Adopting
In-situ Doped Poly-silicon Channel
Microelectronic Engineering
Hsin-Kai Fang, Kuei- Shu Chang-Liao, Chun-Yuan Chen, Po-Hao Chen, Dong-Yan Li, and Chien-Pang Huang, Chang-Hong Shen, and Jia-Min Shieh
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Optimal Process Integration of Gate Insulator and a-Si Layers in Large-Sized a-Si Thin-Film-Transistor
Microelectronic Engineering
Hao-Chieh Lee, Kuei-Shu Chang-Liao, and Yan-Lin Li
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Effects of HfO2/SiON/SiN Stacked Trapping Layer on Operation Characteristics of Poly-Si Flash Memory Devices
Microelectronic Engineering
Hsin-Kai Fang, Kuei-Shu Chang-Liao, Chun-Yuan Chen, and Hao-Wei Ho
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Improved Electrical Characteristics of High-k Gated MOSFETs with Post-Growth Treatment on Interfacial Layer
Microelectronic Engineering
Dun-Bao Ruan, Kuei-Shu Chang-Liao, Chen-Chien Li, Chun-Chang Lu, Yu-Liang Liao, Li-Ting Chen, Yan-Lin Li, Chung-Hao Fu, and Tsung-Lin Hsieh
Conference Papers
Enhanced Sub-20 nm FinFET Performance by Stacked Gate Dielectric With Less Oxygen Vacancies Featuring Higher Current Drive Capability and Superior Reliability
IEEE International Electron Devices Meeting (IEDM)
Y.-H. Chen, C.-Y. Chen, C.-L. Cho, C.-H. Hsieh, and Y.-C. Wu, K.-S. Chang-Liao, Y.-H. Wu
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High Mobility at Ultralow EOT in Ge pMOSFET by Hf-rich Buffer Layer and Microwave Annealing
Chen-Chien Li, Kuei-Shu Chang-Liao, Tzu-Min Lee, Mong-Chi Li, Wei-Fong Chi, Ting-Chun Chen, Tzu-Hsiang Su1, Yu-Wei Chang, Chia-Chi Tsai, Yan-Lin Li, Li-Jung Liu, Chung-Hao Fu, Chun-Chang Lu, and Yao-Jen Lee
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Viable Poly-Si Nanowire Flash Memory Devices with Low Temperature-formed SiO2 Tunneling and Si3N4 Trapping Layers
Chia-Hsin Cheng, Kuei-Shu Chang-Liao, Hsin-Kai Fang, Chun-Yuan Chen, Po-Hao Chen, Dong-Yan Li, Chang-Hong Shen1 and Jia-Min Shieh
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Effects of Microwave Annealing on Ge pMOSFET with Hydrogen-treated Interfacial Layer
Kuei-Shu Chang-Liao, Chen-Chien Li, Li-Jung Liu, Mong-Chi Li, Wei-Fong Chi, Tzu-Min Lee, Tzu-Hsiang Su, Chung-Hao Fu and Yao-Jen Lee