Semiconductor Device Processing & Measuring Lab
National Tsing Hua University, Department of Engineering and System Science
Journal Papers
SiO2 tunneling and Si3N4/HfO2 trapping layers formed with low temperature processes on gate-all-around junctionless charge-trapping flash memory devices
Microelectronics Reliability 2018
Hsin-Kai Fang, Kuei-Shu Chang-Liao, Chia-Hsin Cheng, Po-Yao Lin, Wen-Hsien Huang, Chang-Hong Shen,Jia-Min Shieh
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Improved Electrical Characteristics of ~0.5 nm EOT Ge pMOSFET With GeON Interfacial Layer Formed by NH3Plasma and Microwave Annealing Treatments
IEEE Electron Devices Society 2018
Shih-Han Yi, Kuei-Shu Chang-Liao, Chia-Wei Hsu, Jiayi Huang
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Impact of Ge oxidation states in GeOxinterfacial layer on electrical characteristics of Ge pMOSFETs
International Symposium on VLSI Technology, Systems and Application 2018
Shih-Han Yi, Kuei-Shu Chang-Liao, Chia-Wei Hsu, Jiayi Huang, Tzung-Yu Wu
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Conference Papers
Nucleation limited switching (NLS) model for HfO2-based metal-ferroelectric-metal (MFM) capacitors: Switching kinetics and retention characteristics
Applied Physics Letters 2018​
N Gong, X Sun, H Jiang, KS Chang-Liao, Q Xia, TP Ma
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Effects of Si Content in Si3N4/ZrO2 Stacked Trapping Layer on Operation Characteristics of Poly-Si Gate-All-Around Charge-Trapping Flash Memory Devices
International conference on solid state devices and materials 2018
J.C. Yeh, K.S. Chang-Liao, H.K. Fang, P.G. Wu
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Significant Improvement in Electrical Characteristics of FinFETs by Trilayer High-k Gate Dielectric
International conference on solid state devices and materials 2018
S.H. Hsu, K.S. Chang-Liao, Y.L. Li, C.H. Huang, D.B. Ruan, S.F. Tsai, M.Y. Chen
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Ge Surface Channel Formed by Different Temperature Processes on Characteristics of Poly-Si Charge-Trapping Flash Memory Devices
International conference on solid state devices and materials 2018
C.C. Su, K.S. Chang-Liao, H.K. Fang, Y.C. Yu, W.H. Huang, C.H. Shen, J.M. Hsieh
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High Performance Ge pMOSFET with Nitrided Gate Dielectrics and Microwave Annealing
International conference on solid state devices and materials 2018
C.Y. Kao, S.H. Yi, C.W. Hsu, W.F. Chi, T.M. Li, K.S. Chang-Liao
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Improved Characteristics in 16-nm FinFET by Reducing Oxygen Vacancy in Gate Dielectric with Modified Post-Si Cap/Metallization Annealings
Silicon Nanoelectronics Workshop 2018
C. C. Liu, S. H. Yi, H. I. Yeh, H. J. Chen, C. J. Lin, K. S. Chang-Liao
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Simultaneously High Hole Mobility, Low EOT and Gate Leakage Current of Ge pMOSFET by Engineering Interface and Buffer Layers in Gate Dielectric Stack
Silicon Nanoelectronics Workshop 2018
H. I. Yeh, S. H. Yi, C. C. Liu, J. Huang, T. M. Li, K.S Chang Liao
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Significant Improvement of Operation Speeds in Ω-gate Poly-Si Charge-Trapping Flash Memory Device with Low Temperature-Formed GeO2/SiO2 Tunneling Layer
Silicon Nanoelectronics Workshop 2018
H. –K. Fang , K. S. Chang-Liao , Y. –C. Yu , W. –H. Huang , C. –H. Shen , J. –M. Shieh