The degradation mechanisms that cause time-dependent dielectric breakdown and BTI have been extensively analyzed on MOSFETs with high-κ gate dielectrics, while channel-hot-carrier (CHC) induced degradation is less studied. The CHC degradation is caused by the injection of highly energetic carriers (generated by impact ionization) into the gate dielectric region near the drain side (with nonuniform stress), where defects are generated. Hence, the damage caused by CHC stress leads to a nonuniform trap distribution mainly located above the pinch-off region near the drain, while the trap generation around source side is negligible. To understand and characterize the damage mechanism as well as its related reliability problems, charge-pumping (CP) techniques have been applied to characterize the location of trap generation for both border traps (Nbt) and interface traps (Nit) directly from the measured data. The CP measurement used in this work is keeping the voltage swing constant and only varying the gate pulse frequency to extract the border trap depth profile along high-k. Specially, dynamic drain bias is applied to vary the depletion width of drain junction and the depth profile at various channel locations can thus be determined. The border traps are located within a tunneling distance of gate oxide/Si interface. The electrical behavior of these border traps is similar to that of the interface traps at low frequency (which provides enough transient time for carrier tunneling).