High work function metal gate stacks

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(a) Molybdenum and Titanium based high work function metal gates

Aggressive scaling of channel length and gate oxide thickness in a conventional transistor aggravates the problems of poly-silicon (poly-Si) gate depletion, high gate resistance, high gate tunneling leakage current, and boron penetration into the channel region. As a result, there are immense interests, in metal gates and alternative gate dielectrics with higher permittivity [1]. At this moment, metal gate can greatly reduce the gate sheet resistance, eliminate boron penetration problem, and the most important, eliminate the gate depletion [2]. The traditional poly-silicon gate electrode can make a Fermi-level adjustment by either donor or acceptor implantation. However, the adjustment of the work function (WF) a metal gate is not easily achievable. The required work functions of metal gates for N-channel and P-channel MOS devices are around 4.1–4.2 eV and 4.8–5.0 eV [3].

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在閘極尺度與介電層厚度不斷微縮的趨勢下，傳統的多晶矽閘極面臨著嚴重的問題，包括：

1. 多晶矽閘極空乏層(Poly depletion)。在介電層厚度達到1nm左右時，這個問題變得特別顯著，它會等效地使EOT變大。

2. 硼穿透(Boron penetration)。PMOSFET在閘極摻雜硼以達到所需的閘電極功函數，但經過高溫製成後硼的擴散及穿透問題顯得嚴重，它會造成臨界電壓的不穩定，影響元件的可靠度。

3. 高片電阻值。片電阻值過高會提高元件的功率損耗。

4. Remote charge scattering (RCS)，如圖1.1。此問題會使反轉層內的電荷遷移率下降，進而影響元件的驅動電流。

基於以上幾點傳統多晶矽閘極面臨的問題，金屬閘極在元件尺度微縮的需求下，提供了解答。大多數的金屬閘極皆具備有低的片電阻值；更重要的是，以金屬做為閘電極材料幾乎不會有閘極空乏層及RCS的問題；而藉由各種的功函數調變技術，可以不需要在閘極摻雜硼，也解決了硼穿透的問題。

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(b) Process study of HfO2-based high-k gate dielectric for MOS devices.

The gate leakage current in metal-oxide-semiconductor (MOS) device is getting high with the scaling down of gate oxide thickness. High-k gate dielectric has been proposed to replace SiO2 for MOS device with effective oxide thickness (EOT) below 1.5 nm for suppressing the gate leakage current [1]. The dielectric constant (k) of the HfO2 dielectric, which is about 18~20 [2], is not high enough to reduce the EOT value to below 1 nm for MOS devices. Thus, some exotic higher-k dielectrics have been proposed to replace HfO2.

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VLSI製程技術持續以元件微縮為目標，在CMOS等效氧化層厚度上以被要求微縮至1nm以下。然而，由於以二氧化矽做為介電層微縮到1.5nm以下會導致嚴重的漏電流問題，為了元件持續微縮，改採用高介電常數材料取代二氧化矽做為介電層，但高介電材料與矽基板為非理想接面、界面氧化層的增生使EOT微縮不易與載子遷移率下降，皆是使用高介電材料介電層所帶來的一些新挑戰。